As semiconductor devices become more highly integrated, an isolation distance between devices may become shortened. Accordingly, certain micro-sized devices may not be properly isolated through typical isolation schemes such as a local oxidation of silicon (LOCOS) scheme. To isolate certain micro-sized devices, a trench isolation process may be used. In the trench isolation process, a trench may be formed on a semiconductor substrate, and an insulating material such as a silicon oxide material may be filled in the trench, which may provide device isolation.
In a related art method for manufacturing a semiconductor device having a trench isolation layer, a hard mask layer pattern may be formed on a semiconductor substrate such as a silicon substrate. This may expose a surface of the semiconductor substrate, which may have an isolation layer defining an active area.
The exposed semiconductor substrate may be etched to a prescribed depth, for example by performing an etching process using the mask layer pattern as an etching mask. This may form an isolation trench.
To repair an inner wall of the trench that may have been damaged through the etching process to form the trench, a sidewall oxide layer may be formed on the inner sidewall of the trench. A liner nitride layer may be formed on the resultant structure.
An insulating layer may be deposited on the resultant structure, thereby filling the trench. A planarization process may then be performed, for example using a chemical mechanical polishing (CMP) process to expose a pad nitride pattern. A remaining pad nitride layer pattern may then be removed, which may form the trench isolation layer.
If the trench isolation layer is formed, a gate dielectric layer and a gate conductive layer may be formed in the active region, and a source/drain region may be formed, for example by carrying out a related art ion implantation process.
Such a related art fabricating method of the semiconductor including the trench isolation layer may have a problem. For example, a void may be formed when the trench is filled with the insulating layer. Further, it may take considerable time and require a complex process because of the thermal process used to form the trench isolation layer. Moreover, a residue of a polysilicon layer forming a gate electrode layer may occur since the gate electrode layer may be formed after forming the trench isolation layer.